1. Field of the Invention
Embodiments of the present invention generally relate to a thin film transistor (TFT) and a method for its fabrication.
2. Description of the Related Art
Liquid Crystal Displays (LCDs) are highly utilized in the flat panel display industry. In an LCD, two glass plates are joined together with a layer of liquid crystal material sandwiched therebetween. The substrates are connected to a power source to change the orientation of the liquid crystal material. TFTs have been used to separately address the pixels of the LCD at very fast rates. In the modern display panel, there are millions of pixels which each are separately addressed by a corresponding TFT.
One of the types of TFTs that is used in LCD manufacturing is a bottom gate TFT. A bottom gate TFT contains a gate electrode formed over a substrate, a gate dielectric layer formed over the gate electrode, an active material layer such as amorphous silicon, a doped silicon layer and source and drain electrodes. The active material permits the current to pass from the source to the drain electrode whenever the gate electrode is turned on. Once the current passes to the drain electrode, the pixel is addressed.
The resistivity of the doped silicon layer affects the efficiency of the TFT. The higher the resistivity, the lower the quality of the TFT. Usually, the doped silicon layer is not nearly as thick as the amorphous silicon layer. Therefore, the deposition time for the doped silicon layer is not typically a bottleneck in terms of substrate throughput. Because the doped silicon deposition is not typically a bottleneck, lowering the deposition rate for the doped silicon layer has been considered for depositing lower resistivity doped silicon layers. However, as the processing chambers become larger to produce larger LCDs, it is difficult to achieve both low resistivity across the entire substrate without lowering the deposition rate to such a level that bottlenecking occurs. In fact, the uniformity of the deposition suffers significantly between 400 Angstroms per minute and 1800 Angstroms per minute. As the chamber size gets larger, the deposition non-uniformity range continues to increase.
Therefore, there is a need for a TFT fabrication method that produces a doped silicon layer having both low resistivity and a high enough deposition rate that substrate bottlenecking does not occur.